Software-based Electronic Design Automation (EDA) tools, in general, can process circuit designs through what is referred to as an implementation flow. Processing the circuit design through an implementation flow prepares the circuit design for implementation within a particular integrated circuit (IC). The circuit design can be specified in programmatic form, e.g., as a netlist, as one or more hardware description language files, or the like. A typical implementation flow entails various phases, or stages, such as synthesis, technology mapping, placing, and routing. The resulting circuit design is transformed into a bitstream that, when loaded into the target IC, configures the target IC to implement the circuit design.
Programmable logic devices (PLDs) are a well-known type of IC that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of programmable tiles. These programmable tiles can include, for example, input/output blocks (IOBs), configurable logic blocks (CLBs), dedicated random access memory blocks (BRAM), multipliers, digital signal processing blocks (DSPs), processors, clock managers, delay lock loops (DLLs), and so forth.
Each programmable tile typically includes both programmable interconnect and programmable logic. The programmable interconnect typically includes a large number of interconnect lines of varying lengths interconnected by programmable interconnect points (PIPs). The programmable logic implements the logic of a user design using programmable elements that can include, for example, function generators, registers, arithmetic logic, and so forth.
The programmable interconnect and programmable logic are typically programmed by loading a stream of configuration data into internal configuration memory cells that define how the programmable elements are configured. The configuration data can be read from memory (e.g., from an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the function of the FPGA.
In general, the implementation flow that implements a circuit design within an IC is a serial process in which the output of one stage is provided to the next stage as input. For example, the output of the synthesis stage is provided to the technology mapping stage as input. The output from the technology mapping stage is provided to the placement stage as input, etc. This means that the quality of result determined by a particular stage of the implementation flow depends upon the output of each prior stage.
In illustration, the quality of circuit placement determined by the placement stage will be constrained by the particular technology mapping generated by the technology mapping stage. In conventional EDA tools, only the results are passed on to the next stage. Any intermediate data generated by a stage is discarded. When the results are not satisfactory, the designer must restart the implementation flow from the beginning. For example, if placement or routing is not satisfactory, the designer may be forced to re-synthesize the circuit design using different directives or instructions in the hope that a different circuit structure will result in improved placement and/or routing of the circuit design.